Title :
Actual implementation of multi domain test: Further reduction of cost of test
Author :
Takahashi, Yasuhiro ; Maeda, Akinori ; Ogura, Mitsuhiro
Author_Institution :
S&S Prof. Service, Verigy Japan K.K., Tokyo, Japan
Abstract :
Multi-Sites Test is the popular way to reduce the cost-of-test (COT) at the wafer and the final test. Limitations exist, however, such as the low Multi-Site Efficiency of analog mixed signal tests and the high system price for large pin count devices. Concurrent Test has been implemented to reduce the test time. This test strategy is difficult to implement without the DFT design of the device. The authors introduced the concept of Multi-Domain Test at VTS 2011 and explained that this Multi-Domain Test solves the aforementioned problems and limitations of Multi-Site Test and Concurrent Test. The authors also showed that the COT of Multi-Domain Test is lower than that of Multi-Site Test for high-end SOC devices. This Multi-Domain Test was applied to a mixed signal SOC. Although the Multi-Site Efficiency of the Dual-Site Test was more than 97%, the COT of the Dual-Domain Test was approximately 10% lower than that of the Dual-Site Test.
Keywords :
design for testability; mixed analogue-digital integrated circuits; DFT design; VTS 2011; analog mixed signal tests; concurrent test; cost-of-test; design for testability; dual-domain test; large pin count devices; multi domain test; multi-sites test; Clocks; IP networks; Indexes; Performance evaluation; Power supplies; Sockets; System-on-a-chip;
Conference_Titel :
Test Conference (ITC), 2011 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4577-0153-5
DOI :
10.1109/TEST.2011.6139135
