DocumentCode
3151585
Title
A Fully Automatic Hierarchical Compactor
Author
Entenman, George ; Daniel, Stephen W.
Author_Institution
Microelectronics Center of North Carolina, Research Triangle Park, NC
fYear
1985
fDate
23-26 June 1985
Firstpage
69
Lastpage
75
Abstract
A fully automatic hierarchical compactor has been developed to translate hierarchical, symbolic cell designs into artwork. The hierarchical compactor takes advantage of the fact that a typical hierarchical design uses the same cell in several different places. Each cell is first examined in all of its contexts. The leaf-cell compactor next compacts each leaf-cell to its minimum possible size in its worst-case environment. The last step is to abut instances of the cells according to the original symbolic layout; some grid line spacings may be increased to avoid breaking wires. The compactor is implemented as a set of rule-driven procedures that find all technology dependent information in technology description files. The result of this strategy is a technology-independent compactor that produces compact, error-free artwork.
Keywords
CMOS technology; Circuit synthesis; Compaction; Computer errors; Fabrication; Mesh generation; Microelectronics; Process design; Very large scale integration; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1985. 22nd Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0635-5
Type
conf
DOI
10.1109/DAC.1985.1585914
Filename
1585914
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