DocumentCode
3151624
Title
Logic BIST silicon debug and volume diagnosis methodology
Author
Amyeen, M. Enamul ; Jayalakshmi, Andal ; Venkataraman, Srikanth ; Pathy, Sundar V. ; Tan, Ewe C.
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
2011
fDate
20-22 Sept. 2011
Firstpage
1
Lastpage
10
Abstract
Post silicon speed-path debug and production volume diagnosis for yield learning are critical to meet product time to market demand. In this paper, we present Logic BIST speed-path debug technique and methodology for achieving higher frequency demand. We have developed a methodology for Logic BIST production fail volume diagnosis and presented tester time and memory overhead tradeoffs and optimization for enabling volume diagnosis. Results are presented showing successful isolation of silicon speed-paths on Intel® SOCs.
Keywords
built-in self test; elemental semiconductors; integrated circuit yield; logic testing; silicon; system-on-chip; Intel; SOC; Si; built-in self test; logic BIST silicon debug; production volume diagnosis; volume diagnosis methodology; yield learning; Automatic test pattern generation; Built-in self-test; Databases; Limiting; Production; Silicon; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference (ITC), 2011 IEEE International
Conference_Location
Anaheim, CA
ISSN
1089-3539
Print_ISBN
978-1-4577-0153-5
Type
conf
DOI
10.1109/TEST.2011.6139147
Filename
6139147
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