A fully cell-based design for timing measurement of memory

This work presents a scheme for measuring the timing parameters of a memory´s I/O interface - including the setup/hold time and access time. For setup/hold time measurement, we incorporate a procedure that successively adjusts the timing relation between the clock signal and a controllable valid timing window to estimate the setup/hold time. For access time measurement, we propose a circuit that can capture the worst-case access time of an entire Built-In Self-Test (BIST) session as a pulse width, which is then further measured by traditional time-to-digital converter (TDC). Instead of just reporting a digital code, we also propose a calibration scheme so that we can report not just some digital codes, but also their corresponding absolute values. All the design can be constructed by standard cells. We have implemented it in TSMC 0.18nm CMOS process technology. Simulation results show that the setup time error is less than 3%, the hold time error is 7.5%, and the access time error is 4.4%, with about 6.2% area overhead when the memory size is 4096×64.