Using well/substrate bias manipulation to enhance voltage-test-based defect detection

This paper proposes methods for taking advantage during voltage-based production test of the capability to control well and substrate (body) biases separately from the chip´s VDD and GND. Such control is a by-product of a low-power design strategy that allows parts or all of the chip to go into low-power reduced-leakage states. The proposed test methods use body bias manipulation to increase or decrease transistor threshold voltages. Unlike related methods that rely on weakening transistors, the proposed methods are shown to enhance defect detectability by both weakening and strengthening transistors and by exploiting the ability to weaken/strengthen nfets/pfets separately.