Reusable cryptographic VLSI core based on the SAFER K-128 algorithm with 251.8 Mbit/s throughput

Author

Schubert, A. ; Meyer, V. ; Anheier, W.

Author_Institution

Bremen Univ., Germany

fYear

1998

fDate

8-10 Oct 1998

Firstpage

437

Lastpage

446

Abstract

A VLSI implementation of the symmetric block cipher SAFER K-128 (Secure And Fast Encryption Routine with a Key length of 128 bits) is presented. Possibilities for optimization of the VLSI architecture are explained. The optimizations are based on algorithm-specific properties and lead to considerable hardware reduction. The result is a reusable cryptographic VLSI core that allows a data throughput of 251.8 Mbit/s at a clock frequency of 40 MHz in a 0.7 μm CMOS process. Therefore, the circuit is usable in integrated systems for high-speed data encryption

Keywords

CMOS digital integrated circuits; VLSI; circuit optimisation; cryptography; 0.7 mum; 128 bit; 251.8 Mbit/s; 40 MHz; CMOS; K-128 algorithm; SAFER K-128; Secure And Fast Encryption Routine with a Key length of 128 bits; VLSI; hardware reduction; high-speed data encryption; optimization; reusable cryptographic core; symmetric block cipher; Application software; CMOS process; Circuits; Clocks; Cryptography; Frequency; Hardware; Iterative algorithms; Kernel; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on

Conference_Location

Cambridge, MA

ISSN

1520-6130

Print_ISBN

0-7803-4997-0

Type

conf

DOI

10.1109/SIPS.1998.715806

Filename

715806