DocumentCode :
3151832
Title :
Decomposition of Logic Networks into Silicon
Author :
Healey, Steven T. ; Gajski, Daniel D.
Author_Institution :
Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
fYear :
1985
fDate :
23-26 June 1985
Firstpage :
162
Lastpage :
168
Abstract :
This paper describes a module compiler for decomposing arbitrary functional units of any complexity into abstract cells for customized VLSI layouts. The compiler takes the description of a functional unit as input and builds a dependence graph representation. The graph is then partitioned and the nodes are packed into abstract cell output descriptions. The algorithm will tailor the design to a given area and aspect ratio. Routing is done automatically through the cells.
Keywords :
Algorithm design and analysis; Automation; Computer science; Libraries; Logic; Partitioning algorithms; Routing; Silicon; Spirals; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1985. 22nd Conference on
ISSN :
0738-100X
Print_ISBN :
0-8186-0635-5
Type :
conf
DOI :
10.1109/DAC.1985.1585930
Filename :
1585930
Link To Document :
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