DocumentCode
3151856
Title
Analyzing ATE interconnect performance for serial links of 10 Gbps and above
Author
Lin, Mitchell ; Tolman, Tyler
Author_Institution
Broadcom Corp., Irvine, CA, USA
fYear
2011
fDate
20-22 Sept. 2011
Firstpage
1
Lastpage
8
Abstract
This paper describes a method for analyzing the performance of Automatic Test Equipment (ATE) Device Interface Boards (DIB) for High-Speed Serial Link interface. The procedure requires using only the device under test (DUT) to generate known PRBS TX data and an ATE digitizer to capture the waveform. The information of impulse and frequency response of the signal path can then be obtained by processing this waveform. In addition, data-dependent and periodic jitter can also be calculated. Therefore, without the use of other sophisticated hardware setup, this approach can validate the performance of the fixtures required for testing 10 Gbps Serial Link interfaces and help to identify any signal integrity issues. The proposed method can process waveform data from any instrument and, therefore, can be exploited to analyze signals above 10 Gbps, being limited only by the bandwidth of the instrument itself.
Keywords
automatic test equipment; frequency response; jitter; transient response; ATE digitizer; ATE interconnect performance analysis; PRBS TX data; automatic test equipment; bit rate 10 Gbit/s; data-dependent jitter; device interface boards; device under test; frequency response; high-speed serial link interface; impulse response; periodic jitter; signal integrity; signal path; Clocks; Finite impulse response filter; Fixtures; Instruments; Jitter; Phase locked loops; Relays;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference (ITC), 2011 IEEE International
Conference_Location
Anaheim, CA
ISSN
1089-3539
Print_ISBN
978-1-4577-0153-5
Type
conf
DOI
10.1109/TEST.2011.6139158
Filename
6139158
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