Title :
State of the art low capture power methodology
Author :
Bahl, Swapnil ; Mattiuzzo, R. ; Khullar, Shray ; Garg, Akhil ; Graniello, S. ; Abdel-Hafez, Khader S. ; Talluto, Salvatore
Author_Institution :
Technol. R&D, STMicroelectron., Noida, India
Abstract :
Power consumption during test can be significantly higher than during normal functional mode. This paper presents a low power Automated Test Pattern Generation (ATPG) flow for managing capture power in today´s power critical designs. It introduces a novel method for sequentially enabling the on-chip clock controllers to generate accurate low power ATPG patterns respecting the power specifications of the design. The effectiveness of the method is demonstrated on several industrial designs that show up power issues during test mode.
Keywords :
automatic test pattern generation; integrated circuit testing; ATPG; low capture power methodology; low power automated test pattern generation; on-chip clock controller; power consumption; Automatic test pattern generation; Clocks; Flip-flops; Logic gates; Power demand; Switches; Vectors; capture power reduction; on-chip clock controller; switching activity; vectorless power calculation;
Conference_Titel :
Test Conference (ITC), 2011 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4577-0153-5
DOI :
10.1109/TEST.2011.6139164
