State of the art low capture power methodology

Author

Bahl, Swapnil ; Mattiuzzo, R. ; Khullar, Shray ; Garg, Akhil ; Graniello, S. ; Abdel-Hafez, Khader S. ; Talluto, Salvatore

Author_Institution

Technol. R&D, STMicroelectron., Noida, India

fYear

2011

fDate

20-22 Sept. 2011

Firstpage

1

Lastpage

10

Abstract

Power consumption during test can be significantly higher than during normal functional mode. This paper presents a low power Automated Test Pattern Generation (ATPG) flow for managing capture power in today´s power critical designs. It introduces a novel method for sequentially enabling the on-chip clock controllers to generate accurate low power ATPG patterns respecting the power specifications of the design. The effectiveness of the method is demonstrated on several industrial designs that show up power issues during test mode.

Keywords

automatic test pattern generation; integrated circuit testing; ATPG; low capture power methodology; low power automated test pattern generation; on-chip clock controller; power consumption; Automatic test pattern generation; Clocks; Flip-flops; Logic gates; Power demand; Switches; Vectors; capture power reduction; on-chip clock controller; switching activity; vectorless power calculation;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference (ITC), 2011 IEEE International

Conference_Location

Anaheim, CA

ISSN

1089-3539

Print_ISBN

978-1-4577-0153-5

Type

conf

DOI

10.1109/TEST.2011.6139164

Filename

6139164