Hardware hooks for transition scan characterization

Comprehensive transition scan content was deployed on an Intel^® Itanium^® server microprocessor design, including full coverage patterns for all core logic blocks. Since this was the first time at-speed scan patterns were being planned as a manufacturing screen on an Intel^® CPU core design, the test deployment team needed to ensure that all concerns of over-and under-testing were systematically addressed. A few innovative and novel DFT solutions were deployed to ensure that the post-silicon team had the adequate tools to fully analyze the at-speed scan content. This paper describes these DFT solutions that proved invaluable during this process.