Title :
Hardware hooks for transition scan characterization
Author :
Pant, Pankaj ; Skeels, Eric
Author_Institution :
Intel Corp., Hudson, MA, USA
Abstract :
Comprehensive transition scan content was deployed on an Intel® Itanium® server microprocessor design, including full coverage patterns for all core logic blocks. Since this was the first time at-speed scan patterns were being planned as a manufacturing screen on an Intel® CPU core design, the test deployment team needed to ensure that all concerns of over-and under-testing were systematically addressed. A few innovative and novel DFT solutions were deployed to ensure that the post-silicon team had the adequate tools to fully analyze the at-speed scan content. This paper describes these DFT solutions that proved invaluable during this process.
Keywords :
boundary scan testing; design for testability; logic design; microprocessor chips; DFT solutions; Intel CPU core design; Intel Itanium server microprocessor design; all core logic blocks; at-speed scan content; at-speed scan patterns; comprehensive transition scan content; full coverage patterns; hardware hooks; manufacturing screen; post-silicon team; test deployment team; transition scan characterization; Automatic test pattern generation; Calibration; Clocks; Detectors; Power supplies; Voltage measurement;
Conference_Titel :
Test Conference (ITC), 2011 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4577-0153-5
DOI :
10.1109/TEST.2011.6139166