EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism

Author

Janicki, J. ; Tyszer, J. ; Dutta, A. ; Kassab, M. ; Mrugalski, G. ; Mukherjee, N. ; Rajski, J.

Author_Institution

Poznan Univ. of Technol., Poznan, Poland

fYear

2011

fDate

20-22 Sept. 2011

Firstpage

1

Lastpage

9

Abstract

The paper presents a new channel allocation method for higher Embedded Deterministic Test (EDT) compression in SoC designs comprising isolated cores. It employs a test data reduction technique, which allows cores to interface with ATE through an optimized number of channels. This feature is subsequently used by a new test scheduling and test access mechanisms devised for both the input and output sides. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application scheme and are reported herein.

Keywords

automatic test equipment; channel allocation; data reduction; embedded systems; integrated circuit design; integrated circuit testing; scheduling; system-on-chip; ATE; EDT channel bandwidth management; automated test equipment; channel allocation method; embedded deterministic test compression; industrial SoC designs; pattern-independent test access mechanism; test application scheme; test data reduction technique; test scheduling; Logic gates; Multiplexing; Multiprocessor interconnection; Switches; System-on-a-chip; Testing; Vectors;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference (ITC), 2011 IEEE International

Conference_Location

Anaheim, CA

ISSN

1089-3539

Print_ISBN

978-1-4577-0153-5

Type

conf

DOI

10.1109/TEST.2011.6139170

Filename

6139170