Hierarchical Analysis of IC Artwork with User Defined Abstraction Rules

Hierarchical DRC and component extract offer many advantages but no one form of hierarchical analysis fits all situations. This paper introduces hierarchical analysis in which the user specifies how abstract representations of cells are formed, how they are checked, and what to do if a violation is detected. This allows one analysis program (with different rules) to use the designer´s hierarchy for a wide variety of different analyses. In particular, analyses that had been difficult in previous schemes (cross coupling capacitances, terminals in the center of cells, multi-layer interconnects) can now be handled hierarchically.