An Algorithm for Design Rule Checking on a Multiprocessor

Design rules and the problem of design rule checking are introduced. The critical problem of design rule checking is the execution time required to check a complete chip. Proposed solutions try to take advantage of hierarchical aspects of a layout. The algorithm presented in this paper proposes a different approach. Observing that design rule checking is a very local operation, a method is described for partitioning a design for checking on a multiprocessor. An implementation is described and results are given for runs on a single processor. These results indicate that speedup proportional to the number of processors is possible.