Addressable Arrays Implemented with One Metal Level for MOSFET and Resistor Variability Characterization

Author

Ketchen, Mark B. ; Bhushan, Manjul ; Costrini, Greg

Author_Institution

T.J. Watson Res. Center, IBM Res., Yorktown Heights, NY

fYear

2009

fDate

March 30 2009-April 2 2009

Firstpage

13

Lastpage

18

Abstract

Addressable array test structures for rapid collection of statistical distributions of MOSFET parameters and parasitic resistances are described. A unique feature of these designs is that they require only one level of metal, yet are compact for placement in the scribe line for early process learning. MOSFET measurements are made over full range of I-V characteristics including leakage currents of individual devices in the sub-threshold region. A modular approach for test structure integration and parallel testability enables high efficiency in design and data acquisition.

Keywords

MOSFET; data acquisition; leakage currents; semiconductor device measurement; semiconductor device models; semiconductor device testing; statistical distributions; I-V characteristics; MOSFET measurement; MOSFET parameter statistical distribution; addressable array test structure integration; data acquisition; one level metal design; parallel testability; parasitic resistance; resistor variability characterization; scribe line; subthreshold region leakage current; Circuit testing; Current measurement; Decoding; MOSFET circuits; Resistors; Semiconductor device modeling; Semiconductor process modeling; Silicon on insulator technology; System testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2009. ICMTS 2009. IEEE International Conference on

Conference_Location

Oxnard, CA

Print_ISBN

978-1-4244-4259-1

Type

conf

DOI

10.1109/ICMTS.2009.4814600

Filename

4814600