DocumentCode
3152670
Title
A Circuit Comparison System for Bipolar Linear LSI
Author
Sakata, Takeshi ; Kishimoto, Aritoyo
Author_Institution
Second LSI Division, NEC Corporation, Kawasaki, Japan
fYear
1985
fDate
23-26 June 1985
Firstpage
429
Lastpage
434
Abstract
This paper describes a new LST layout verification system which compares two circuits. One is extracted from LSI layout, and the other is an original circuit diagram. This system is also capable of giving layout error information to designers. In particular, this system is applicable to bipolar linear LSIs containing a variety electrical elements.
Keywords
Circuits; Data mining; Design automation; Large scale integration; Manuals; National electric code; Redundancy; Signal design; Signal processing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1985. 22nd Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0635-5
Type
conf
DOI
10.1109/DAC.1985.1585976
Filename
1585976
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