DocumentCode
3152919
Title
Test Structure for High-Voltage LD-MOSFET Mismatch Characterization in 0.35 um HV-CMOS Technology
Author
Posch, Werner ; Murhammer, Christian ; Seebacher, Ehrenfried
Author_Institution
Austriamicrosystems AG, Unterpremstatten
fYear
2009
fDate
March 30 2009-April 2 2009
Firstpage
96
Lastpage
101
Abstract
A characterization setup for high voltage (HV) LD-MOSFET mismatch and variability determination is presented. The according test chip was successfully realized in 0.35 um HV-CMOS technology. Devices are aligned in rows and columns for gate and drain bias multiplexing and special HV-switches for voltages up to 50 V are controlled by externally generated digital signals. Automatic DC measurements can be performed on up to 4992 HV-NMOSFETs, providing variability data for both, short and long distance matching characterization.
Keywords
CMOS integrated circuits; MOSFET; integrated circuit testing; HV-CMOS technology; automatic DC measurement; drain bias multiplexing; high-voltage LD-MOSFET mismatch characterization; size 0.35 mum; test structure; Doping; Electrical resistance measurement; Electrodes; FETs; Performance evaluation; Predictive models; Semiconductor device measurement; Switches; Testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 2009. ICMTS 2009. IEEE International Conference on
Conference_Location
Oxnard, CA
Print_ISBN
978-1-4244-4259-1
Type
conf
DOI
10.1109/ICMTS.2009.4814618
Filename
4814618
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