Sigma-Delta ADC Clock Jitter in Digitally Implemented Receiver Architectures.

The analog-to-digital (AD) converter in modern multi-band multi-mode software defined radios plays a very important role. This paper will show how the specifications for the clock of a sigma-delta AD-converters can be derived. In contrast to literature, where clock jitter (in ps_rms) is specified, a different approach will be taken, in which the frequency dependent spurious of the clock signal can be calculated in the case of a GSM receiver