Metal and Dielectric Thickness: a Comprehensive Methodology for Back-End Electrical Characterization

Back-end-of-line (BEOL) process variation is becoming more and more important since technology is scaling down and increases its complexity. On-chip capacitances and resistances are strongly dependent on the BEOL geometrical configuration so it is really important to have an accurate characterization of the metal and dielectric thickness. Interconnect parasitic modelling by means of LPE tool (Layout Parasitic Extraction) or semi-analytic approximation can´t neglect the impact of metal (dielectric) thickness variations. The focus of this work is to provide an accurate, simple and suitable for parametric testing methodology to electrically measure metal (dielectric) thickness, mandatory for a useful characterization and control of a technology.