DocumentCode :
3153305
Title :
A Test Structure for Assessing Individual Contact Resistance
Author :
Liu, F. ; Agarwal, K.
Author_Institution :
IBM Austin Res. Lab., Austin, TX
fYear :
2009
fDate :
March 30 2009-April 2 2009
Firstpage :
201
Lastpage :
204
Abstract :
Accurate measurement of contact resistance is crucial for advanced nanometer CMOS processes. An equally important requirement is to measure contact resistances in the same micro-environment as the device-under-test (DUT) will be used in real designs. With complicated interactions among various layout shapes in nanometer CMOS processes, test structures with adequate scalability is needed. In this paper we present a scalable contact resistance measurement structure, which can accommodate tens of thousands of DUTs. The measurement results from a 65 nm CMOS technology are also presented.
Keywords :
CMOS integrated circuits; MOSFET; contact resistance; nanoelectronics; semiconductor device measurement; semiconductor device testing; CMOS layout shape; advanced nanometer CMOS process; device-under-test; microenvironment; scalability; scalable contact resistance measurement; size 65 nm; test structure; CMOS process; CMOS technology; Contact resistance; Electrical resistance measurement; Plugs; Position measurement; Proposals; Shape measurement; Testing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures, 2009. ICMTS 2009. IEEE International Conference on
Conference_Location :
Oxnard, CA
Print_ISBN :
978-1-4244-4259-1
Type :
conf
DOI :
10.1109/ICMTS.2009.4814641
Filename :
4814641
Link To Document :
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