Analysis of Timing Failures Due to Random AC Defects in VLSI Modules

This paper presents an analytical model for projecting the yield loss due to random delay defects for modules or VLSI packages containing multiple semiconductor chips. A module to be analyzed is characterized by distribution of path delays. Statistical analysis is applied to obtain the distribution of delays caused by defects in logic circuits of LSI chips. The model uses these two distributions to calculate the probability that a module contains a path that does not meet the system timing requirements. All inputs to the model can be obtained much earlier than the availability of modules for actual testing. Therefore expected module yield loss due to delay defects can be projected before the modules are actually manufactured.