Title :
A study of loop unrolling for VLIW-based DSP processors
Author :
Sair, Suleyman ; Kaeli, David R. ; Meleis, Waleed
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
With the growing popularity of DSP and their associated applications, cost-effective software development has become a major issue. High-level language compilers are becoming more commonplace in the DSP world. While these compilers can generate correct code for DSP architectures, there remains considerable room for performance improvements. This paper addresses issues related to DSP compilation, focusing specifically on unrolling techniques proposed for VLIW-based DSP architectures
Keywords :
compiler generators; digital signal processing chips; DSP compilation; VLIW-based DSP processors; compiler generator; cost-effective software development; high-level language compilers; loop unrolling; Application software; Computer architecture; Costs; Digital signal processing; High level languages; Pipeline processing; Processor scheduling; Programming; Reduced instruction set computing; Registers;
Conference_Titel :
Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7803-4997-0
DOI :
10.1109/SIPS.1998.715814
