A Transistor-Level Logic-with-Timing Simulator for MOS Circuits

VTIsim is a transistor-level simulator for MOS circuits which provides logic simulation together with approximate timing estimates based on layout information. Two novel features enhance the accuracy of simulation: node states are represented as voltages rather than as logic states, and node transitions are modeled as voltage ramps rather than as steps taking place at a fixed instant. This paper describes the major features of the simulator, some issues in its design, and the benefits and problems of using it.