Charge-gain program disturb mechanism in split-gate flash memory cell

Intrinsic charge-gain program disturb mechanism in split-gate flash memory cells has been identified based on simulation results and experimental data obtained on memory arrays fabricated with 0.18 mum SuperFlash^reg technology. It was shown that program disturb has the same nature under all three program disturb conditions existing in NOR flash memory array, and is a result of band-to-band tunneling caused by high electric field in the split-gate channel area and subsequent hot electron injection. We also analyzed reliability aspects of this program disturb mechanism on 16-Mbit memory arrays, and found no substantial effect of 10 program-erase cycles on disturb characteristics. The understanding of intrinsic program disturb mechanism is important for split-gate cell technology scaling as well as for optimization of cell design and operating conditions.