An approach to accelerate deformable image registration by FPGA based mutual information calculation and pattern search optimization

Real time computation of deformation fields is essential for automated deformable image registration algorithms for time critical applications. However, the computational power of current microprocessors is not sufficient for real time computation of it; therefore requiring implementations using either massively parallel computers or application-specific hardware accelerators. A sequential pipeline for the calculation of mutual information is presented which allows a faster implementation of deformable image registration process. Hierarchical image subdivision based registration algorithm with mutual information (MI) as the cost function is used. A low memory parallel implementation of MI calculation is proposed here. The final objective of image registration is achieved by a software and hardware implementation, where host computer performs pattern search optimization (PSO) and FPGA calculates MI required for optimization.