A performance evaluation of a RISC-based digital signal processor architecture

As the complexity of DSP (digital signal processing) applications increases, the need for efficient processor architectures and compilers also grows. RISC-based DSP processors not only have general-purpose registers and orthogonal instruction formats to support compiler-friendliness, but also contain several DSP processor-specific features, such as single cycle MAC (multiply-and-accumulate), direct memory access, automatic address generation, and hardware looping, to execute arithmetic and data-intensive DSP operations efficiently. We evaluate the performance effects of each architectural add-on feature using DSP benchmarks. Benchmark programs are compiled using modified C compilers that accommodate the DSP processor-specific features. We also compare the performances with those of superscalar RISC architectures having two, three, and four issue capabilities in one clock cycle. Finally, an application-level performance comparison is conducted using a QCELP vocoder program