Title :
Logic Synthesis and Optimization Benchmarks for the 1986 Design Automation Conference
Author :
De Geus, Aart J.
Author_Institution :
GE Calma Company, Research Triangle Park, NC
Abstract :
In order to compare logic synthesis and optimization systems, a set of benchmarks has been submitted to a number of authors. The results obtained are reported in the present proceedings. This short paper introduces the benchmarks as well as a set of criteria to measure the quality of logic synthesis systems.
Keywords :
Acceleration; Availability; Circuit synthesis; Circuit testing; Design automation; Design optimization; Logic circuits; Logic design; Programmable logic arrays; Timing;
Conference_Titel :
Design Automation, 1986. 23rd Conference on
Print_ISBN :
0-8186-0702-5
DOI :
10.1109/DAC.1986.1586071
