A Logic Verifier Based on Boolean Comparison

This paper proposes a logic VERIFIER, which verifies the correctness of the gate-level design by comparing it with the behavioral description. An improved Boolean comparison technique, which assures the absence of errors without designer´s assist, is proposed. The partitioning and the minimization techniques are effective to reduce the storage required, and indispensable to verify practical sized circuits. If the design is judged incorrect, the system analyzes the result and show the area containing errors. Experimental results have proved that the VERIFIER can detect design errors completely, and indicate them to the designers in comprehensible form.