DocumentCode
3154674
Title
A Heuristic Chip-Level Test Generation Algorithm
Author
Barclay, Daniel S. ; Armstrong, James R.
Author_Institution
Electrical Engineering Department, Virginia Tech, Blacksburg, VA
fYear
1986
fDate
29-2 June 1986
Firstpage
257
Lastpage
262
Abstract
An algorithm is given for generating tests from chip-level functional descriptions. The algorithm uses a chip-level fault model to define faults and fault sensitization requirements, and uses the hardware description language (HDL) definition to solve for the test vector. Artificial intelligence techniques of goal trees and rule databases are used to implement the algorithm in ProLog. The goal types and solving strategies are outlined. The current, partial ProLog implementation is discussed.
Keywords
Artificial intelligence; Automatic testing; Automation; Computational modeling; Databases; Hardware design languages; Pins; Signal processing algorithms; Very high speed integrated circuits; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1986. 23rd Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0702-5
Type
conf
DOI
10.1109/DAC.1986.1586098
Filename
1586098
Link To Document