A Unified Treatment of PLA Faults by Boolean Differences

The calculation of test patterns for PLAs is an expensive and time consuming task if a general purpose test pattern generation programm is used. A unified treatment of faults in PLAs and a test pattern generation algorithm based on the calculation of Boolean differences is given in this paper. Calculating the difference between the Boolean functions of the faulty and the fault free circuit guarantees that a test for a given fault is found if it exists. By tayloring the algorithm to the specific structure of programmable logic arrays a powerful tool for the test pattern calculation for PLAs is obtained. An important feature of the method is the ease of incorporating different fault assumptions.