DocumentCode
3155038
Title
Incremental Logic Synthesis through Gate Logic Structure Identification
Author
Shinsha, T. ; Kubo, T. ; Sakataya, Y. ; Koshishita, J. ; Ishihara, K.
Author_Institution
Systems Development Laboratory, Hitachi, Ltd., Kawasaki-shi, Japan
fYear
1986
fDate
29-2 June 1986
Firstpage
391
Lastpage
397
Abstract
This paper describes incremental logic synthesis for supporting function logic changes in the physical design stage of digital systems. The incremental logic synthesis is distinguished from logic synthesis in the respect that it updates only gate logic components, which must be changed due to the function logic changes, in the physically optimized gate logic structure. For making the incremental logic synthesis feasible, a gate logic structure identification and editing system has been developed with a corresponding gate matrix method as its core. This system has greatly contributed to the increase in design efficiency of the very large computer series M68XH.
Keywords
Automatic logic units; Delay systems; Design optimization; Digital systems; Job design; Laboratories; Logic design; Logic gates; Production; Software engineering;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1986. 23rd Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0702-5
Type
conf
DOI
10.1109/DAC.1986.1586119
Filename
1586119
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