Automated Extraction of SPICE Circuit Models from Symbolic Gate Matrix Layout with Pruning

VLSI designers have made extensive use of SPICE simulation to analyze timing-critical circuits such as critical paths and clock distribution networks. Rigorous modeling of resistive and capacitive parasitics and transistors is required for these timing-critical circuits. Unfortunately the conventional circuit extractors have been unable to model wiring resistance and extracting the essential subcircuits, and therefore have required extensive manual editing. Manual editing is so complicated that designers frequently opt to code manually from computer plots of mask information, a process which requires days of work to extract and debug only one path. This process is acceptable for coding those critical paths which do not involve large networks. To manually code an extensive subcircuit, such as a clock distribution network, would be unthinkable. In this paper, we present a new technique for generating SPICE codes for user specified subcircuits directly from Gate-Matrix symbolic files. We have pruned off non-essential elements from symbolic files, generated tables of electrical elements and their connections of the subcircuit in concern, and from there, generated SPICE codes which include relevant resistive and capacitive loading. An application of this technique for the clock distribution network in WE[R] 32100 CPU is described.