BIST-based fault diagnosis in the presence of embedded memories

Author

Savir, Jacob

Author_Institution

Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA

fYear

1997

fDate

12-15 Oct 1997

Firstpage

37

Lastpage

47

Abstract

An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free

Keywords

built-in self test; fault diagnosis; logic testing; BIST; BIST-based fault diagnosis; Postlogic; Prelogic; automatic test pattern generation; embedded memories; fault simulation; logic embedding; Built-in self-test; Circuit faults; Circuit testing; Computer aided manufacturing; Discrete event simulation; Fault diagnosis; Jacobian matrices; Logic testing; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-8206-X

Type

conf

DOI

10.1109/ICCD.1997.628847

Filename

628847