Frequency synthesis using pulse width locked loop

Implemented fractional-N frequency synthesizer architecture based upon Pulse Width Locked Loop technique eliminates the need for ¿¿ modulator within the loop while preserving the frequency resolution and accuracy of such synthesizers. Eliminating the modulator allows the designer to optimize the synthesizer loop bandwidth without any constraint imposed by the modulator. The loop operates by locking precisely the output frequency to a control voltage. Implemented loop occupies an area of 650 ¿m by 630 ¿m in 0.35 ¿m CMOS process and draws 383 ¿A from a single 3.3 V supply. It covers a frequency range of 4-70 MHz with 76 Hz resolution and has a measured phase noise performance of 104 dBc/Hz at 1 MHz offset with the worst spurious signal level of -70 dBc.