Title :
A single chip for optimal edge detection
Author :
Zarka, N. ; Akil, M.
Author_Institution :
Sci. Studies & Res. Centre, Syria
Abstract :
We present the architecture of a single chip for optimal edge detection of blurred and noisy 2D images. The chip has a systolic architecture which processes, in real time, any second order recursive filters. The chip is designed in 1.5 μ CMOS technology using COMPASS CAD tools. The chip area is 66.5 mm2, the number of transistors is about 182000 and the power consumption is 750 mW. This chip can be used in medical image edge detection
Keywords :
CMOS digital integrated circuits; circuit CAD; digital signal processing chips; edge detection; image processing equipment; medical image processing; recursive filters; systolic arrays; 1.5 micron; 1.5 mu CMOS technology; 750 mW; COMPASS CAD tools; blurred 2D images; chip area; medical image edge detection; noisy 2D images; optimal edge detection; power consumption; second order recursive filters; single chip architecture; systolic architecture; transistors;
Conference_Titel :
Image Processing and its Applications, 1995., Fifth International Conference on
Conference_Location :
Edinburgh
Print_ISBN :
0-85296-642-3
DOI :
10.1049/cp:19950708
