• DocumentCode
    3155510
  • Title

    A New Routing Algorithm and Its Hardware Implementation

  • Author

    Watanabe, Takumi ; Sugiyama, Yoshi

  • Author_Institution
    NTT Electrical Communications Laboratories, Kanagawa, Japan
  • fYear
    1986
  • fDate
    29-2 June 1986
  • Firstpage
    574
  • Lastpage
    580
  • Abstract
    Presented is a new parallel processing wire routing algorithm that can control path quality in two point connections and find a quasi-minimum Steiner tree for multi-point connections. A parallel rip-up technique for finding a candidate path which blocks an unconnected net is also presented. These routing algorithms are implemented on a two-dimensional array processor, the AAP-1. It is experimentally shown that the average AAP-1 execution time per net using the routing algorithm is 100 msec in a 256X256 grid.
  • Keywords
    Adaptive arrays; Communication system control; Design automation; Engines; Hardware; Laboratories; Parallel processing; Routing; Very large scale integration; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1986. 23rd Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-8186-0702-5
  • Type

    conf

  • DOI
    10.1109/DAC.1986.1586145
  • Filename
    1586145
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3155510