A Rule-Based Logic Circuit Synthesis System for CMOS Gate Arrays

This paper presents a CMOS gate-array version of Digital System Design Language/Synthesis eXpert (DDL/SX), a rule-based system for logic circuit synthesis. The system inputs technology-independent functional diagrams, and automatically generates conventional technology-dependent logic diagrams in order to eliminate time-consuming and error-prone tasks in logic design. Because the synthesis process was not clear enough to establish a fixed algorithm, a rule-based approach was adopted to develop the system. This approach made it easy to incrementally improve the system´s capabilities by adding, modifying, or deleting design knowledge represented as rules. Experimental use of the system revealed that the automatically generated logic design is almost as good as a manual design, and the design time is reduced by a factor of four.