DocumentCode :
3155857
Title :
A Rule-Based Approach to Unifying Functional and Fault Simulation and Timing Verification
Author :
Ghosh, Sudip
Author_Institution :
Computer Systems Laboratory, Stanford University, Stanford, CA
fYear :
1986
fDate :
29-2 June 1986
Firstpage :
677
Lastpage :
682
Abstract :
A novel approach to design verification is presented that is based on a new methodology for modeling and verifying digital designs. The verification methodology unifies functional and fault simulation and timing verification into one general rule-based framework wherein functional, fault, and timing characteristics of digital designs are expressed through a set of rules. Consequently, models of new devices and for new types of simulations may be introduced into the verification system with relative ease. Introducing other types of simulations into the verifier would require expressing the appropriate characteristics of digital devices in the form of rules. This approach has been verified in the experimental RDV [GS84] system at Stanford University and the hardware-description language used is Ada [AD83]. Unification of functional and fault simulation and timing verification is made possible by a combination of distributed approaches to modeling and scheduling.
Keywords :
Computational modeling; Computer simulation; Context modeling; Design for experiments; Hardware; Knowledge based systems; Laboratories; Libraries; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1986. 23rd Conference on
ISSN :
0738-100X
Print_ISBN :
0-8186-0702-5
Type :
conf
DOI :
10.1109/DAC.1986.1586163
Filename :
1586163
Link To Document :
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