DocumentCode
3156054
Title
Associative-memory-based prototype LSI with recognition and on-line learning capability and its application to handwritten characters
Author
Imafuku, Wataru ; Sakakibara, Shogo ; Kawabata, Akio ; Ansari, Tania ; Mattausch, Hans Jürgen ; Koide, Tetsushi
Author_Institution
Res. Inst. for Nanodevice & Bio Syst., Hiroshima Univ., Higashi-Hiroshima, Japan
fYear
2009
fDate
7-9 Jan. 2009
Firstpage
627
Lastpage
630
Abstract
In the presented research on VLSI-system design for handwritten-character learning and recognition, an associative memory architecture for searching the most similar data among previously stored reference data is applied. The chosen associative memory achieves high speed, low power consumption and small implementation area due to a mixed digital-analog fully-parallel nearest-match search circuitry. To recognize new data, a learning capability based on the concept of short/long-term memory which tries to mimic the function of the human brain is realized. For improvement of the recognition rate, we propose a reference-data-optimization algorithm that averages the recognized input patterns for each stored reference object and updates the corresponding reference pattern periodically. We evaluated the proposed intelligent VLSI-design method for the application of hand-written character learning and recognition. Therefore, test-chip in 0.18 um CMOS technology was designed to demonstrate the proposed algorithm and design method. The simulated processing capability of this test-chip amounts to 0.3 million input-character images per second.
Keywords
CMOS integrated circuits; VLSI; character recognition equipment; content-addressable storage; handwritten character recognition; memory architecture; CMOS technology; VLSI system design; associative memory based prototype LSI; digital-analog fully parallel nearest match search circuitry; handwritten character learning; handwritten character recognition; intelligent VLSI design method; online learning capability; reference data optimization algorithm; short/long term memory; size 0.18 micron; Associative memory; CMOS technology; Character recognition; Energy consumption; Handwriting recognition; Large scale integration; Memory architecture; Pattern recognition; Prototypes; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Signal Processing and Communication Systems, 2009. ISPACS 2009. International Symposium on
Conference_Location
Kanazawa
Print_ISBN
978-1-4244-5015-2
Electronic_ISBN
978-1-4244-5016-9
Type
conf
DOI
10.1109/ISPACS.2009.5383762
Filename
5383762
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