DocumentCode
315615
Title
Analytical energy dissipation models for low power caches
Author
Kamble, Milind B. ; Ghose, Kanad
Author_Institution
Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
fYear
1997
fDate
18-20 Aug. 1997
Firstpage
143
Lastpage
148
Abstract
We present detailed analytical models for estimating the energy dissipation in conventional caches as well as low energy cache architectures. The analytical models use the run time statistics such as hit/miss counts, fraction of read/write requests and assume stochastical distributions for signal values. These models are validated by comparing the power estimated using these models against the power estimated using a detailed simulator called CAPE (CAache Power Estimator). The analytical models for conventional caches are found to be accurate to within 2% error. However, these analytical models over-predict the dissipations of low-power caches by as much as 30%. The inaccuracies can be attributed to correlated signal values and locality of reference, both of which are exploited in making some cache organizations energy efficient.
Keywords
CMOS memory circuits; SRAM chips; cache storage; circuit analysis computing; CAPE simulator; CMOS SRAM cell; analytical energy dissipation models; hit/miss counts; low energy cache architectures; low power caches; read/write requests fraction; run time statistics; static RAM; stochastical distributions; Analytical models; Computer architecture; Computer science; Energy dissipation; Energy efficiency; Microprocessors; Permission; Random access memory; Read-write memory; State estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design, 1997. Proceedings., 1997 International Symposium on
Conference_Location
Monterey, CA, USA
Print_ISBN
0-89791-903-3
Type
conf
Filename
621264
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