A Delay Test System for High Speed Logic LSI´s

This paper presents a delay test system which detects the delay faults located in LSI chips. Fault model and the measure of fault coverage are defined. This system features easy to use operation for providing the test data, including fail safe design to violation of scan design rule, quick turn around time for test data generation, and consideration for delay fault analysis. The delay test is applied to the LSIs for M-68X series computers and justified its effectiveness to assure computer system´s maximum performance.