DocumentCode
315633
Title
Analysis of power consumption in memory hierarchies
Author
Hicks, Patrick ; Walnock, Matthew ; Owens, Robert Michael
Author_Institution
Pennsylvania State Univ., University Park, PA, USA
fYear
1997
fDate
18-20 Aug. 1997
Firstpage
239
Lastpage
242
Abstract
In this paper, we note and analyze a key trade-off: as the complexity of caches increases (higher set-associativity, larger block size, and larger overall size), the power consumed by a cache access increases. However, because the hit rate also increases, the number of main memory accesses decreases and thus the power consumed by a memory access decreases. Recent papers which consider the power consumption of caches tend to ignore hit rates. This is unfortunate, because it is undesirable to have energy-efficient caches which are also very slow. Hit rates also play a key role in truly evaluating the energy efficiency of a cache, because low hit rates lead to more frequent main memory accesses which consume more power than cache accesses.
Keywords
VLSI; cache storage; memory architecture; microprocessor chips; portable computers; block size; caches; energy-efficient caches; hit rate; main memory accesses; memory hierarchies; power consumption; set-associativity; Decoding; Energy consumption; Energy efficiency; Fabrication; Microprocessors; Mobile communication; Mobile computing; Permission; Power generation;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design, 1997. Proceedings., 1997 International Symposium on
Conference_Location
Monterey, CA, USA
Print_ISBN
0-89791-903-3
Type
conf
Filename
621290
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