Low power architecture for high speed infrared wireless communication system

A high performance and low power architecture is devised for a 4 Mbps infrared wireless communication system dedicated to mobile computing. In this architecture 4PPM (4-Pulse Position Modulation) infrared signals detected by an infrared receiver are digitized into TTL interface level pulses, and the digitized pulses are demodulated by a 1-bit digital demodulator. To extend the range of the link length, a 4PPM demodulator is synthesized to implement a demodulation algorithm which is constructed so as to accommodate the output tolerance of the infrared receiver. A experimental results show that the proposed 4 Mbps infrared communication system can achieve an error free link in the range of 0-140 cm at power consumption of 245 mW and 65 mW for transmitting and receiving, respectively. The communication controller is integrated in a 0.6 /spl mu/m CMOS standard-cell chip, which contains 10,015 transistors on a 12 mm/sup 2/ die.