Title :
A parity check matrix design for Irregular LDPC codes with 2K block length
Author :
Prasartkaew, Chutima ; Choomchuay, Somsak
Author_Institution :
Coll. of Data Storage Technol. & Applic., King Mongkut´´s Inst. of Technol. Ladkrabang, Bangkok, Thailand
Abstract :
This paper outlines the work on another design of a parity check matrix for Irregular LDPC codes. The design is based on the pattern of Modified Array and Interleaved Modified Array LDPC codes. The application of matrix transposition Quasi-cyclic shifting has resulted in the reduction of 1´s. The designed matrix is suitable for codes with short and medium block lengths. The code rate of 0.56 at the BER of 10-4 is obtained.
Keywords :
matrix algebra; parity check codes; 2K block length; interleaved modified array LDPC codes; irregular LDPC codes; matrix transposition quasicyclic shifting; parity check matrix design; Bit error rate; Block codes; Decoding; Educational institutions; Error correction codes; Memory; Parity check codes; Signal design; Signal processing; Signal to noise ratio;
Conference_Titel :
Intelligent Signal Processing and Communication Systems, 2009. ISPACS 2009. International Symposium on
Conference_Location :
Kanazawa
Print_ISBN :
978-1-4244-5015-2
Electronic_ISBN :
978-1-4244-5016-9
DOI :
10.1109/ISPACS.2009.5383779
