A gate resizing technique for high reduction in power consumption

With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. In this paper we propose a post-mapping technique that can reduce the power dissipation by performing gate resizing. This technique consists of replacing some gates of the circuit with devices in a complete cell library having smaller area and, therefore, smaller gate capacitance with lower power consumption. The slack time of each gate in the circuit is first computed to determine the set of gates that can be down-sized. A global optimization procedure based on integer linear programming and the simplex method is then applied to determine the best overall gate resizing solution. Experimental results on benchmark circuits have shown a power reduction in the range from 2.8 to 27.9% compared to circuits without resizing. The most relevant features of our technique are that it is applicable to large digital circuits and gives an optimal resizing solution in a short computation time (no more than 15.8 seconds).