Title :
Device and technology optimizations for low power design in deep sub-micron regime
Author :
Chen, Kai ; Hu, Chenming
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
This report, based on the most recent analytical and experimental studies of CMOS scaling and gate delay models, reexamines the fundamental design quantities such as driving current, I/sub dsat/, propagation delay, t/sub pd/, and switching energy, E, and investigates device optimization issues in deep sub-micron regime. Empirical I/sub dsat/ equations and device optimization guidelines with gate oxide, channel length and power supply scaling as well as interconnect loading are extracted.
Keywords :
MOSFET; semiconductor device models; MOSFET model; channel length; deep sub-micron CMOS device scaling; driving current; gate delay; gate oxide; interconnect loading; low power design; optimization; power supply; propagation delay; switching energy; Analytical models; Degradation; Design optimization; MOSFET circuits; Permission; Power supplies; Predictive models; Propagation delay; Semiconductor device modeling; Threshold voltage;
Conference_Titel :
Low Power Electronics and Design, 1997. Proceedings., 1997 International Symposium on
Conference_Location :
Monterey, CA, USA
Print_ISBN :
0-89791-903-3
