An architecture evaluation system based on the datapath structure and parallel constraint

We present an architecture evaluation system which aids designer optimization of the datapath configuration and the instruction set of embedded custom DSPs. Given a datapath structure, it evaluates the performance in terms of an estimated number of steps to execute the target program on the datapath. A concept of “parallel constraint” is newly introduced, which enables evaluation of the impact of instruction format design on the performance without explicitly specifying the instruction format. Thus, designers can evaluate the performance of architectural variations in the early design stage. We applied the system to some actual designs of signal processors. We show some applications of the system to actual signal processors