Fast RSSI circuit using novel power detector for wireless communication

This paper describes a fast received signal strength indicator (RSSI) circuit for wireless communication application. It is developed using a novel power detector with a fast settling time. The power detector is consisted of a variable gain amplifier (VGA), a peak detector, and a comparator in a closed loop. The VGA achieved a wide gain range in a closed loop form. For the peak detector, a fast settling time and small ripple are obtained using the orthogonal characteristics of quadrature signals. In 0.18 mum CMOS process, the RSSI value settles down in 20 mus with power consumption of 20 mW, and the maximum ripple of the RSSI is 30 mV. The proposed RSSI circuit is fabricated with a Personal Handy-phone System (PHS) receiver. The active area is 0.8 mm times 0.8 mm.