• DocumentCode
    315671
  • Title

    Reconfiguration of degradable VLSI/WSI arrays under the constraint of row bypass and column rerouting

  • Author

    Low, C.P.

  • Author_Institution
    Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
  • Volume
    3
  • fYear
    1997
  • fDate
    9-12 Jun 1997
  • Firstpage
    1604
  • Abstract
    This paper examine the problem of reconfiguring two dimensional VLSI/WSI arrays via the degradation approach. In this approach, all elements are treated uniformly and no elements are dedicated as spares. The goal is to derive a fault-free subarray T from the defective host array such that the dimensions of T are larger than some specified minimum. This problem is known to be NP-complete under the constraint of row bypass and column rerouting. However, we show that a special case of the reconfiguration problem is optimally solvable in linear time. Using this result, a new fast and efficient reconfiguration algorithm is proposed for the general problem. Empirical study shows that the new algorithm indeed produce good results in terms of the percentages of harvest and degradation of VLSI/WSI arrays
  • Keywords
    VLSI; cellular arrays; circuit layout CAD; computational complexity; integrated circuit layout; network routing; wafer-scale integration; NP-complete problem; column rerouting constraint; degradable VLSI/WSI arrays; degradation approach; fault-free subarray; reconfiguration algorithm; row bypass constraint; two dimensional arrays; Degradation; Hardware; Heuristic algorithms; Logic arrays; Switches; Turning; Very large scale integration; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
  • Print_ISBN
    0-7803-3583-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.1997.621438
  • Filename
    621438