Title :
A low power 100 MHz all digital delay-locked loop
Author :
Kim, Bum-Sik ; Kim, Lee-Sup
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
Abstract :
All digital DLL is designed for synchronization of high frequency VLSI system with low power consumption and small area. Two new design method features are presented. First, the operation is described by Verilog HDL and verified. Second, using the circuit level simulations and optimizations, low power consumption and high speed is achieved. The simulation results show that the power consumption is 3.2 mW at 100 MHz, 2.0 V supply voltage without driver buffers; the area is 0.1 mm2 and the proposed DLL has no jitter
Keywords :
VLSI; circuit analysis computing; circuit optimisation; delay circuits; hardware description languages; synchronisation; 100 MHz; 2.0 V; 3.2 mW; Verilog HDL; all digital delay-locked loop; circuit level simulations; circuit optimizations; high frequency VLSI system; high-speed ICs; power consumption; synchronization; Circuit simulation; Delay; Design methodology; Driver circuits; Energy consumption; Frequency synchronization; Hardware design languages; Jitter; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.621500
