An integrated design methodology for asynchronous circuit engineering

In this paper the computer-aided design flow of asynchronous interface circuits is discussed. The different steps of the complete design flow are briefly touched upon. As novel contributions, we propose a methodology, starting from a formal Petri-net based specification model that allows analysis and validation of these specifications and resulting in VHDL based netlists. Therefore we present general technology mapping methods in order to use their results for a comprehensive synthesis process. Using the presented methods and integrating them into our object oriented design environment, a complete asynchronous design flow is supported. The presented system provides links to existing state of the art asynchronous and synchronous circuit synthesis tools and implements a consistent design methodology for asynchronous circuit engineering